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Altera_Forum
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17 years ago

QII 8.0SP1 gives Error 10028 with SystemVerilog using modport

Hi All, I am trying to synthesize several SystemVerilog modules that declare interfaces and then use them to connect to each other. One interface module shows Error 10028 : Can't resolve m...
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Altera_Forum
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17 years ago

Hi vjAlter,

Yes, two different interfaces would work too as long as the output name is different.

I agree that the current level of support is better than nothing at all but not being on par with Synopsys tools makes it hard to run ASIC code on FPGAs.

RAUL