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Altera_Forum
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17 years ago

QII 8.0SP1 gives Error 10028 with SystemVerilog using modport

Hi All, I am trying to synthesize several SystemVerilog modules that declare interfaces and then use them to connect to each other. One interface module shows Error 10028 : Can't resolve m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks, I just also found out that I need to separate the interface declarations into two separate files each one with one output to be able to proceed in synthesis. So in the end I have:

if1.sv

========

interface if1...

logic reset;

modport rcv1 (output reset...

=======

if2.sv

========

interface if2...

logic reset;

modport rcv2 (output reset...)

============

vs. before

if.sv

===========

interface if...

logic reset;

modport rcv1 (output reset...)

modport rcv2 (output reset...)

=========

Thanks for the prompt reply.