Honored Contributor
Honored ContributorAfter thinking about this for a bit, the pseudo-bottom up approach described here is one way that I could proceed to make sure that different submodules aren't fighting over the same resources: forum/showthread.php?t=814&highlight=optimize+specific+paths
Though I am also alternatively interested in manual assignment via altera_attribute assignments directly in the HDL. Page 16-69 in the QII handbook shows Example 16–117, showing how to change a Quartus Setting (?) in Verilog HDL. I'd like to do this with different Quartus Setting, but I'm having trouble doing this. Before trying to use this procedure to promote clock lines to specific resources, I wanted to use this procedure to assign a module to a specific Logic Lock region like so: (* altera_attribute = {"-name LL_ENABLED ON;-name LL_ORIGIN LAB_X50_Y34_N0;-name LL_WIDTH 19;-name LL_HEIGHT 9" }*) module foo( ....... Looking at Chip Planner after fitting, Quartus actually places the module somewhere else, though. Am I using this procedure incorrectly? Thanks.
