Pull Down

What's driving the pin and why do you need it pulled-down? I'm assuming whatever is supposed to be the driver isn't actually driving for some reason. Is it the FPGA that needs to be driven low when it goes into user mode? What about using the weak pull-up and then inverting the input?

If you can't invert the input(because you'd be changing the functionality once the external driver is active), use the weak pull-up on the pin. If the pin drives a register, make sure that it powers up to 0(which will happen automatically). Have another register which is the clock enable for this register. This CE register will also power up to 0, and its D input will be driven by VCC. It will be clocked by a falling edge on the input pin. So until your external driver becomes active and drives a negative clock edge, the input register will have its clock enable turned off and will be ignoring the external input.

(There's also a solution if there is no input register, but it involves a mux and will probably have a glitch)

Will it work? Most likely.

Is it hokey? Absolutely.

Be sure to disable Power-Up Don't Care, so the clock enable register doesn't get synthesized to power up to 1 and get synthesized out.

(Note that I don't know what you're situation is, and there's probably a better solution if you provide more details. What's the external driver? Why isn't it driving? Why does the input need to be pulled down when it comes out of reset? Is the input a clock or data signal? Anything else that you think might be relevant.)