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I'm still learning but isn't the long path simply because of the 12.1ns required tsu? It seems to me like QII simply delayes the signal to line it up roughly 12ns before the output clock CLK_OUT_48 (although it slightly misses the mark).
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For clock setup (FPGA input tsu, FPGA output tco corresponding to your external device tsu, and internal paths), Quartus does not delay signals. Quartus tries to minimize the data path delay.
Quartus delays signals only for clock hold (FPGA input th, FPGA output minimum tco corresponding to your external device th, and internal paths), and it does so only if "Optimize hold timing" has an appropriate setting.
Note that your 12.1 ns is subtracted from the data required path (the line with the oExt type). The bigger your external device required tsu (which means, the smaller the FPGA allowed tco), the smaller the data required time will be, and the more Quartus will need to try to make the data required path quicker.
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