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Your inst3|inst4|lpm_ff_component|dffs[0] register and the inst3|inst2 combinational LUT apparently are being placed quite a way from the N_SLWR device pin. Along the lines of what was said in Rysc's first post, this is likely because these nodes are fed by or also feed something else placed somewhere else, with the other connection pulling them away from the pin because the Fitter was trying to meet the timing requirement on that connection too.
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I'm still learning but isn't the long path simply because of the 12.1ns required tsu? It seems to me like QII simply delayes the signal to line it up roughly 12ns before the output clock CLK_OUT_48 (although it slightly misses the mark).
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To see whether it would be OK to place these nodes closer to the pin without breaking another path using these nodes, place the register in the LAB adjacent to the pin or place a LogicLock region beside the pin with the register-to-pin path assigned to the region. If the register and/or combinational node feed more than one pin, place them in the center of all those pins.
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I will study this option. But surely this would break the tsu=12.1ns and th=3.6ns requirements?
Honored Contributor
