Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- ... The clock comes from the PLL and the timing IS met in fast/slow models unless other (unrelated) I/O is constrained (like i'm trying to do now). ... The fact that timing *can* be met tells me that the fitter does a worse job when it has to deal with other I/O. --- Quote End --- I realize that variation in the routing is probably the entire cause of your negative slack, but have you checked the Fitter report to see whether the output delay chain is set differently for the data and/or clock when you get negative slack versus when you don't? I think the Fitter uses course timing estimates when it picks delay chain values. Setting the output delay chain manually for data and clock outputs might help. If the delay chains are done early in fitting as I think, then that is long before the routing stage. Manually setting the delay chains might make no difference if the entire problem is bad choices by the router. One or two routing hops being different in the routing stage can have a big effect on slack. --- Quote Start --- Can i lock a certain routing (that works) before adding constraints for other I/O? --- Quote End --- Individual routing lines can be controlled in an .rcf file (routing constraints file), but you probably wouldn't want to do that. Maybe you can isolate the portion of the design with the troublesome outputs into its own design partition and use incremental compilation to preserve the routing for that partition after you get good results for it. --- Quote Start --- Does the *order* constraints are listed in the SDC file matter? --- Quote End --- The order can matter for some things. If you had a problem related to the order of constraints, you would probably have messages (in at least some cases they are warnings) saying something about an order-dependent choice made by TimeQuest. Maybe a simple way to test whether two different SDC constraint orderings are equivalent would be to run write_sdc with each order. If the two .out.sdc files are identical, then the order doesn't matter. Use the -expand argument for write_sdc. The -expand argument might be necessary to check for the order of derive_pll_clocks versus manual clock constraints. That's an order-dependent thing for which a change was made a few versions ago.