Proper method to constrain internal paths in TimeQuest?

The interface should be source synchronous since both the clock and signal is generated inside the FPGA. The clock comes from the PLL and the timing IS met in fast/slow models unless other (unrelated) I/O is constrained (like i'm trying to do now).

Can i lock a certain routing (that works) before adding constraints for other I/O? The fact that timing *can* be met tells me that the fitter does a worse job when it has to deal with other I/O. Does the *order* constraints are listed in the SDC file matter?

Thanks,

/John.