Proper method to constrain internal paths in TimeQuest?

Yes, you probably can't meet that timing. Note that your clock period is ~20ns, and you're using 15.7ns of that externally(not counting any board delay. So that only gives you a ~4ns window to get data out of the FPGA.

The second constraint is that it gets out greateer than 3.6ns(i.e. min Tco) in the fast model. Taking a general guesstimate, any delay in the fast model will be twice that in the slow model. So if it just makes 3.61ns to get off chip in the fast model, it takes 7.2ns in the slow model, which just makes your setup. But it's easy for the delays to be more than 2x, especially if you're not in the fastest speed grades(which don't affect the fast model, but make the slow model slower, and the "spread" larger.)

Note that you do have board delays, so if the're 1ns, you can decrease your minimum by that, which shoudl help. The only other major thing I can think of is to modify the clock delays(skew them, make them source synchronous, etc.)