Honored Contributor
Honored Contributor- What device and speed grade? It helps to see if 3ns hops are that long
- I don't see a Location column. Is this a post-fit timing analysis? It's tough to tell if the placement is bad - The set_max_delay shouldn't make any difference, as Quartus already knows it needs to get the data out before the latch clock hits the external register. Adding a set_max_delay doesn't provide anymore information. The two things I can think of are: 1) This node fans out to other IO or something. Do a report_timing -setup -detail full_path -npaths 200 -from SdramFifo...lpm_ff_component..|dffs[0] and see how many paths this goes to. Then highlight all the paths in the Summary view and right-click Locate Path to Chip Planner. In there you can hit on the Expand button a few times to break out the hops and IC if it helps, but basically if this feeds other stuff on the other side of the chip or something, then you've got conflicting placement requirements(it needs to feed two separate locations). 2) You have a conflicting timing requirements. Right-click on the path and do a report_timing -hold -detail full_path. Then change the set_operating_condition to the min model. Re-run the hold check and see how much it makes timing by. The fitter will add routing delays to meet hold requirements, which works directly against your setup requirement.
