Hi,
so I did not go through all ICs to understand what they're doing, but it looks to me like an awful lot of hacks for timing etc. Just as an example, U3, R15 and C4 form some sort of delay line; the whole "Clock Generator" part is just a multivibrator chip, with the external circuitry doing some fine-tuning I suppose. Then I see a couple of cascaded gates, which is typically done to achieve some delay, and that's hard to reproduce with CPLDs, which are nowadays orders of magnitudes faster.
I'd say you have two options. The first one is to re-build the thing 1:1, just for the sake of having a retro device in a new shell. You have to modify the circuit to work with 3.3V, or whatever your CPLD can do. Also, I expect that some parts of the circuit simply won't work at all because they probably relied on more subtle behavior of certain ICs, but that's just a gut feeling (there's a lot of analog and digital mixed). You asked about diodes: well, just for example look at D5. It goes to pin 8 of U26 via a resistor. That pin 8 is an output from what I saw in the datasheet. So it looks like it's purpose is to pull the node between R16 and R17 low when pin 8 of U26 is low, but keeps that node unaffected (oscillating, it's part of the clock generator) when pin 8 is high. The diode is needed. Oh, and you asked about caps: look for example at C3. That's the frequency tuning cap for 74121. You need that in that particular circuit, but when using a CPLD (a purely digital chip), you're probably better off just using a counter on a fast clock to tune the frequency.
Option 2: with a powerful tool like VHDL or Verilog at your hands, I'd just re-design the thing completely digital. With all the limitations that I mentioned about option 1, this looks like a better solution. Less retro, though, just the same functionality. You'll have to waste some registers on counters for emulating some timing, yes.
Best regards,
GooGooCluster
Honored Contributor
