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Currently I have all extra modules in the (main) code and just comment/uncomment the connections between them. Unfortunately I also need to comment/uncomment different sections in the .sdc file to get proper timing analysis.
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Why don't you use parameters (Verilog) or generics (VHDL)?
Tcl scripts can be used for synthesis and simulation. Those scripts can set the values of the generics/parameters. The .sdc file is just Tcl, so it can also use the generics/parameters (or different files can be included based on the generics/parameters).
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An other thing I'd like to have, is some user-readable version information about the image. So how may I have different text strings and version numbers in each image?
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I use;
* Board identification
* FPGA identification (for multiple FPGAs on a board)
* Design ID
* Build timestamp (passed in as a Tcl generic)
These are all 32-bit registers. Tcl can then format the IDs into strings - no need for the strings to be stored in hardware.
You can also add read-only registers for all the generics/parameters. That way your software can read the design ID, then the generics, and then provide the appropriate hardware-specific functions.
Cheers,
Dave
Honored Contributor
