Honored ContributorCurrently I am working on an openCL project. It works in simulation, but when I compiled for hardware using Quartus, it could not finish even with a whole weekend! (it's estimated to consume 76% DSP and 78% BRAM) Could the reason be that the generated verilog file is not synthesizable?
Honored ContributorIf it wasnt synthesisable, it would have failed fairly quickly.
These long compilations often stem from RAMs not be inferred using embedded memory, but being built from registers instead. These can make compillation times explode - so make sure your rams are actually rams Other things that increase compile time: 1. Not enough system ram, as virtual ram is very very slow 2. Higher resource usage. Using more than 50% of the chip can make compillation take longer 3. Effort multipliers tend to increase compile time and after about 5x they tend to increase compile time without much benefit. Assuming you have enough RAM for whatever chip you're building for, a full chip (>50% often counts as "full" for routing purposes) should complete in hours, not days.Honored ContributorThanks for your reply! I will look into your point!! A few hours ago I reduced the size of my project and compiled again, and the Quartus compilation has moved into stage Quartus asm. Do you think this is a good sign?
Honored ContributorASM is the assembler that creats a programming file for your chip. This should only take a few minutes and means the main compilation has finished.
