Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Project a Counter with a Dephased Clock.

Hello, I am working in a Project in a Power Eletronic's laboratory and I am stucked in a part of the project. I am suposed to built a high-frequency PWM to get a high resolution in the converti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

if I understood you.

you want to divide 100MHz clock into 3MHz.

accumulate 3 modulo 100 i.e:

0+3

3+3

6+3

...

96+3

99+3 => 2

2+3

5+3

...

watch count value if < 50 then output '0' else output '1'

This division is fractional and corrects itself on average