Programming MAX 10 with .mif

I simplified the RTL considerably, and now it's just outputting zeroes over UART :confused:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
entity UTTM is
  port ( 
    CPU_RESETn     : in  std_logic;                    -- 3.3V LVCMOS
    CLK_50_MAX10   : in  std_logic;                    -- 2.5V
    CLK_25_MAX10   : in  std_logic;                    -- 2.5V
    CLK_LVDS_125_p : in  std_logic;                    -- 2.5V
    CLK_10_ADC     : in  std_logic;                    -- 2.5V
    USER_LED       : out std_logic_vector(4 downto 0); -- 1.5V
    USER_PB        : in  std_logic_vector(3 downto 0); -- 1.5V
    USER_DIPSW     : in  std_logic_vector(4 downto 0); -- 1.5V
    UART_TX        : out std_logic                     -- 2.5V
  );
end entity UTTM;
architecture RTL of UTTM is
  -- UART
  component uart_simple port (
    i_clk          : in  std_logic;
    I_clk_baud_count : in  std_logic_vector(15 downto 0);
    i_reset        : in  std_logic;
    i_txdata       : in  std_logic_vector(7 downto 0);
    i_txsig        : in  std_logic;
    o_txrdy        : out std_logic;
    o_tx           : out std_logic
    );
  end component; 
  -- RAM
  component RAM port (
    data       : in std_logic_vector (11 downto 0);
    rd_aclr    : in std_logic  := '0';
    rdaddress  : in std_logic_vector (13 downto 0);
    rdclock    : in std_logic ;
    rden       : in std_logic  := '1';
    wraddress  : in std_logic_vector (13 downto 0);
    wrclock    : in std_logic  := '1';
    wren       : in std_logic  := '0';
    q          : out std_logic_vector (11 downto 0)
    );
  end component RAM;
  -- FSM
  type statetype is (S0, S1, S2);
  signal state, nextstate  : statetype;
  signal statecode         : std_logic_vector(7 downto 0) := (others => '0');
  -- UART
  signal txdata            : std_logic_vector(7 downto 0) := (others => '0');
  signal txsig             : std_logic := '0';
  signal txrdy             : std_logic := '0';
  signal rdaddress         : std_logic_vector (13 downto 0);
  signal rden              : std_logic;
  signal q                 : std_logic_vector (11 downto 0);
  signal TX_activation     : std_logic := '0';
  signal TX_completion     : std_logic := '0';
begin
  uart_instance : uart_simple port map (
    I_clk            => CLK_LVDS_125_p,
    I_clk_baud_count => X"32DD", -- 9600 bps @ 125 MHz clock
    --I_clk_baud_count => X"043D", -- 115200 bps @ 125 MHz clock
    --I_clk_baud_count => X"0088", -- 921600 bps @ 125 MHz clock
    I_reset          => not CPU_RESETn,
    I_txdata         => txdata,
    i_txsig          => txsig,
    o_txrdy          => txrdy,
    O_tx             => UART_TX
  );
  -- RAM
  RAM_inst : RAM port map (
    data      => (others => '0'),
    rd_aclr   => not CPU_RESETn,
    rdaddress => rdaddress,
    rdclock   => CLK_LVDS_125_p,
    rden      => rden,
    wraddress => (others => '0'),
    wrclock   => '0',
    wren      => '0',
    q         => q
  );
  -- may need to add a first-run variable as RAM has not yet been read out for first UART transmission
  tx_RAM_process : process (CLK_LVDS_125_p, CPU_RESETn) 
  variable i : integer := 0;
  begin
    if CPU_RESETn = '0' then
      i             := 0;
      txdata        <= (others => '0');
      txsig         <= '0';
      rden          <= '0';
      rdaddress     <= (others => '0');
      TX_completion <= '0';
    elsif rising_edge(CLK_LVDS_125_p) then
      if txrdy = '1' and TX_activation = '1' then
        if i <= (12500-1) then -- output loop begin
          i             := i + 1;
          txdata        <= q(11 downto 4);
          txsig         <= '1';
          rden          <= '1';
          rdaddress     <= std_logic_vector(to_unsigned(i,14));
          TX_completion <= '0';
        else
          i             := 0;
          txdata        <= (others => '0');
          txsig         <= '0';
          rden          <= '0';
          rdaddress     <= (others => '0');
          TX_completion <= '1';
        end if;                -- output loop end
      end if;
    end if;
  end process;
  FSM_clock_process : process (CLK_LVDS_125_p, CPU_RESETn) is
  begin
    if rising_edge(CLK_LVDS_125_p) then
      if CPU_RESETn = '0' then
        state <= S0;
      else
        state <= nextstate;
      end if;
    end if;
  end process FSM_clock_process;
  FSM_io_process : process (CPU_RESETn, state, TX_completion, USER_PB) is
  begin
    if CPU_RESETn = '0' then
      TX_activation        <= '0';
      nextstate            <= S0;
      USER_LED(3 downto 0) <= "1111";
    else
      -- default assignments
      TX_activation        <= '0';
      nextstate            <= state;
      USER_LED(3 downto 0) <= "1111";
      case state is
        -- idle state after reset
        when S0 =>
          USER_LED(3 downto 0) <= "1110";
          if USER_PB = "1110" then
            TX_activation <= '1';
            nextstate <= S1;
          end if;
        when S1 =>
          USER_LED(3 downto 0) <= "1100";
          if TX_completion = '1' then
            TX_activation <= '0';
            nextstate <= S2;
          end if;
        when S2 =>
          USER_LED(3 downto 0) <= "1000";
          if USER_PB = "0111" then
            nextstate <= S0;
          end if;
      end case;
    end if;
  end process FSM_io_process;
end architecture RTL;