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Honored ContributorAlex,
The RAM is instantiated in ADC_RAM which in turn is instantiated in UTTM.library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
entity ADC_RAM is port (
clock : in std_logic; -- input from higher level
async_reset : in std_logic; -- input from higher level
ADC_inclock : in std_logic; -- input from pin
ADC_in : in std_logic_vector (5 downto 0); -- input from pin
ADC_oe : out std_logic; -- output to pin
ADC_SCL : out std_logic; -- output to pin
ADC_SDA : inout std_logic; -- bidirecional to pin
ADC_SENn : out std_logic; -- output to pin
ADC_OVR : in std_logic; -- input from pin
rdaddress : in std_logic_vector (13 downto 0); -- input from higher level
rden : in std_logic := '1'; -- input from higher level
q : out std_logic_vector (11 downto 0); -- output to higher level
activation : in std_logic; -- input from higher level
completion : out std_logic); -- output to higher level
end entity ADC_RAM;
architecture RTL of ADC_RAM is
-- RAM
component RAM
port
(
data : in std_logic_vector (11 downto 0);
rd_aclr : in std_logic := '0';
rdaddress : in std_logic_vector (13 downto 0);
rdclock : in std_logic ;
rden : in std_logic := '1';
wraddress : in std_logic_vector (13 downto 0);
wrclock : in std_logic := '1';
wren : in std_logic := '0';
q : out std_logic_vector (11 downto 0)
);
end component RAM;
-- FSM
type statetype is (S0, S1, S2, S3, S4);
signal state, nextstate : statetype;
-- Misc Clock domain:
signal clock_Core : std_logic; -- Core
signal clock_ADC : std_logic; -- ADC
signal clock_ADC_config : std_logic; -- ADC
signal reset_Core : std_logic; -- Core
signal reset_ADC : std_logic; -- ADC
signal RAM_filled_ADC : std_logic; -- ADC
signal LVDStoRAM_en_ADC : std_logic; -- ADC
signal RAM_filled_Core : std_logic; -- Core
signal LVDStoRAM_en_Core : std_logic; -- Core
signal ADC_wait_start : std_logic; -- ADC
signal ADC_wait_done : std_logic; -- ADC
signal ADC_config_start_Core : std_logic; -- Core
signal ADC_config_start_ADC : std_logic; -- ADC
signal ADC_config_done_Core : std_logic; -- Core
signal ADC_config_done_ADC : std_logic; -- ADC
-- RAM
signal data_sig : std_logic_vector (11 downto 0);
-- signal rdaddress_sig : std_logic_vector (13 downto 0);
-- signal rdclock_sig : std_logic;
-- signal rden_sig : std_logic;
signal wraddress_sig : std_logic_vector (13 downto 0);
-- signal wrclock_sig : std_logic;
signal wren_sig : std_logic;
-- signal q_sig : std_logic_vector (11 downto 0)
begin
-- RAM
RAM_inst : RAM port map (
data => data_sig, -- internal
rd_aclr => reset_Core, -- port through async_reset_sync_release process
rdaddress => rdaddress, -- port
rdclock => clock_Core, -- port through signal
rden => rden, -- port
wraddress => wraddress_sig, -- internal
wrclock => clock_ADC, -- port through signal
wren => wren_sig, -- internal
q => q -- port
);
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
entity UTTM is
port (
CPU_RESETn : in std_logic; -- 3.3V LVCMOS
CLK_50_MAX10 : in std_logic; -- 2.5V
CLK_25_MAX10 : in std_logic; -- 2.5V
CLK_LVDS_125_p : in std_logic; -- 2.5V
CLK_10_ADC : in std_logic; -- 2.5V
HSMC_CLK_IN_p : in std_logic; -- LVDS (CLKOUTM) / PINS: V10, V9
HSMC_RX_D_p : in std_logic_vector(5 downto 0); -- LVDS / PINS: AB7, Y4, AB5, W13, AB15, Y16, AB6, Y3, AA5, W12, AA14, AA15
HSMC_SCL : out std_logic; -- 2.5V / PIN: Y18
HSMC_SDA : inout std_logic; -- 2.5V / PIN: AA19
HSMC_SENn : out std_logic := '0'; -- 2.5V / PIN: Y7
HSMC_OVR : in std_logic; -- 2.5V / PIN: Y8
);
end entity UTTM;
architecture RTL of UTTM is
component ADC_RAM port (
clock : in std_logic;
async_reset : in std_logic;
ADC_inclock : in std_logic;
ADC_in : in std_logic_vector(5 downto 0);
ADC_oe : out std_logic;
ADC_SCL : out std_logic;
ADC_SDA : inout std_logic;
ADC_SENn : out std_logic;
ADC_OVR : in std_logic;
rdaddress : in std_logic_vector(13 downto 0);
rden : in std_logic;
q : out std_logic_vector(11 downto 0);
activation : in std_logic;
completion : out std_logic
);
end component;
-- FSM
type statetype is (S0, S1, S2, S3);
signal state, nextstate : statetype;
signal statecode : std_logic_vector(7 downto 0) := (others => '0');
-- ADC/RAM
signal RAM_address : std_logic_vector(13 downto 0) := (others => '0'); -- output
signal RAM_read_en : std_logic := '0'; -- output
signal RAM_dataout : std_logic_vector(11 downto 0); -- input
signal ADC_activation : std_logic := '0'; -- output
signal ADC_completion : std_logic; -- input
--constant ADC_wait_cycles : natural := 13; -- "wait for valid ADC data" delay = 100 ns
begin
ADC_RAM_instance : ADC_RAM port map (
clock => CLK_LVDS_125_p,
async_reset => not CPU_RESETn,
ADC_inclock => HSMC_CLK_IN_p,
ADC_in => HSMC_RX_D_p,
ADC_oe => open,
ADC_SCL => HSMC_SCL,
ADC_SDA => HSMC_SDA,
ADC_SENn => HSMC_SENn,
ADC_OVR => HSMC_OVR,
rdaddress => RAM_address,
rden => RAM_read_en,
q => RAM_dataout,
activation => ADC_activation,
completion => ADC_completion
);LIBRARY ieee;USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM IS
PORT
(
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rd_aclr : IN STD_LOGIC := '0';
rdaddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rden : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END RAM;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
BEGIN
q <= sub_wire0(11 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "CLEAR1",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
init_file => "../../source/RAM_init.mif",
intended_device_family => "MAX 10",
lpm_type => "altsyncram",
numwords_a => 12500,
numwords_b => 12500,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "CLEAR1",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
rdcontrol_reg_b => "CLOCK1",
widthad_a => 14,
widthad_b => 14,
width_a => 12,
width_b => 12,
width_byteena_a => 1
)
PORT MAP (
aclr1 => rd_aclr,
address_a => wraddress,
address_b => rdaddress,
clock0 => wrclock,
clock1 => rdclock,
data_a => data,
rden_b => rden,
wren_a => wren,
q_b => sub_wire0
);
