Programmer's Verification

Hi,

you mean the checkbox "Verify" in the Quartus Programmer? It only seems to be available for flash memory, e.g. CPLD config or user flash memory. According to the Quartus help (http://quartushelp.altera.com/current/master.htm#mergedprojects/program/pgm/pgm_image.htm (http://quartushelp.altera.com/current/master.htm#mergedprojects/program/pgm/pgm_image.htm)), it verifies the contents of the memory against your programming file. Therefore, yes, it reads it back, but only for the purpose of verifying it. Doesn't look like you can download the data stream from the CPLD back to your computer.

As far as I know, Altera FPGAs have no facility to read back the data stream, which is why this option is not available for FPGAs. However, the FPGAs have some special pins to indicate programming errors.

Best regards,

GooGooCluster