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Altera_Forum
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15 years ago

Programmable delay line in CycloneIII

hi all, I'm trying to develop a programmable delay line into a Cyclone III FPGA, because a I would create a pulse with a specific length, on rising edge of "ingresso". My idea is this: http://i5...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

What are the constraints for your design. From the rising edge of an input, how much jitter and delay can you tolerate on the output pulse. How much delay resolution and length do you need on the output signal? Ideally, what you are trying to do, shouldn't be done in a design.

Thanks, just curious.