Programmable delay line in CycloneIII

hi FvM and ronp,

as FvM says, I discard the PLL way, because input isn't at fixed repetition rate; also programmable IO delays are not good for me because are fixed at compile (or is there a method to exchange it on the fly?).

External delay lines are ok, in fact in the previous version of board that I'm developing, two '195 are used for this purpose, but since I added a FPGA for other purpose, I'm trying to eliminate most of off the shelf chips.

coming back to my idea, I thought that lcells are sensitive to variations of Vdd or temperature, but interconnections between cells are almost independent. Is this right?

Then putting all the mux (designed so that there is an equal number of gates between each input and output, then the same "nominal" delay) in a single LogicArrayBlock, delays between mux part are negligible rather connection between "smalldelay" lcell and mux that are in separate LAB.

Yesterday I read some on timing constraints, but I am a newbie... I try with a SDC file with

set_min_delay -from  -through }] -to  1.000ns
set_min_delay -from  -through }] -to  2.000ns
set_max_delay -from  -through }] -to  2.000ns
set_max_delay -from  -through }] -to  3.000ns

inserting it into TimeQuestAnalyzer into project settings and fitting but nothing... I also removed LogicLock Regions (I think perhaps it would place gates in other LAB to meet constraints but it doesn't with LogicLock) but another time nothing...

Could suggest me the right procedure to write time constraints and to fit project that meets them?

sorry for long post... any other tips are welcome!!!

Ale