Programmable delay line in CycloneIII

As far as I understood the intention of the original post, none of the suggested methods would help in this case, except for the external delay element. There are various options to generate variable delays and pulsewidths by analog circuits. The challenge is to implement it in an FPGA. PLL dynamic phase shift is a good tool, but it's only applicable for clocks with a fixed frequency.

Logic delay lines at first imply a large variation over pvt (process, voltage, temperature), so usually a calibration would be necessary. Not equally spaced delays are unavoidable due to the LAB granularity of the FPGA. Monotonicity is mainly a matter of how the delay chain output is switched. The mux, that has to be translated to multiple LUTs and the respective routing are causing the problems, I think.

I'm curious, if timing constraints and timing driven synthesis would be able to achieve at least monotonic behaviour.

I would try to implement a structure for the delay chain, that promises monotonicity by design, e.g. as considered in the initial post of this thread. The input should be implemented as global signal in this case.

http://www.alteraforum.com/forum/showthread.php?t=26995