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Altera_Forum
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8 years ago

Program the Altera MAX-V CPLD using JTAG

I have previously only been working with Xilinx FPGAs, so I need some help to flash to Altera MAX-V which for me seems to be a bit different from the Xilinx flash procedure. The goal is to flash the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Are you using a development kit or your own board? With a dev kit, there should be a JTAG (10 pin, 2 rows of 5) or USB blaster connection. It does not require pin assignments in the Pin Planner since they are hard pins. If you're using your own board, you must have a 10-pin connection to bring the JTAG connection out for USB Blaster.