Lets get started.
You need to use one of numeric_std or std_logic_arith. numeric_std library has the to_integer function in it, so you need to include it.
Secondly - there are loads of problems with this code. This code is riddled with latches and code that is going to have differences in simulation and real hardware.:
1. The "enter" signal - in the first process you have it as an asynchronous enable, but you havent included it in the sensitivity list. Sensitivity lists are ignored for synthesis and this process is going to cause you problems.
2. Every time Y changes you are setting the values of reg to constants - why?
3. PC is being incremented only when Y changes to fetch. But because it is in an asynchronous process, on real hardware it would be trying to increment a infinite number of times - whenever Y = fetch it keeps adding 1 until it moves out of fetch. In simulation it should only add once, but on real hardware it will not work because it will be trying to add one an infinite number of times.
4. Looking at this code, it looks like you're a software programmer. Before you write VHDl you should try drawing your circruit diagram out in registers and gates. And then describe it in VHDL. VHDL is not a programming language.