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OK, thanks for answer. I have indeed understood it correctly then (your answer supports what I already knew of this).
Reason for asking: In some people's VHDL I see this - a signal that only changes upon a clock edge but appears in the sensitivity list so I was wondering why this may be the case... Guess they needn't have!
wait until...? That's a testbench thing no?
Anyway, thank again!
Andy
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wait unti clk = '1';
is same as if rising_edge(clk) then
and leads to registered assignments.
This is not wait for 1 ns; ...etc very popular with beginners and Unis
Honored Contributor
