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Altera_Forum's avatar
Altera_Forum
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11 years ago

Processes sensitivity list question

Hello, OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL.. SIGNAL slv_Clock : STD_LOGIC; SIGNAL slv_Sig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

OK, thanks for answer. I have indeed understood it correctly then (your answer supports what I already knew of this).

Reason for asking: In some people's VHDL I see this - a signal that only changes upon a clock edge but appears in the sensitivity list so I was wondering why this may be the case... Guess they needn't have!

wait until...? That's a testbench thing no?

Anyway, thank again!

Andy