Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- Hello, OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL..
SIGNAL slv_Clock : STD_LOGIC;
SIGNAL slv_Signal : STD_LOGIC;
proc_DoSomething : PROCESS(slv_Clock, slv_Signal)
BEGIN
IF RISING_EDGE(slv_Clock) THEN
IF slv_Signal = '0' THEN
--Do something cool
END IF;
END IF;
END PROCESS proc_DoSomething;
Question: What would the point of putting the signal slv_signal in the PROCESS sensitivity list be for? Thanks again! Andy --- Quote End --- No need. process is activated by clk only. If slv was outside clk(before if rising... then yes you need it