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First you need to know if it is 'X' or 'U'. When you have a vector with X or U 's in it, Modelsim will sometimes replace the vector value by 'X'. Looking at the individual bits should tell you which one of those two it is.
'U' means uninitialized. All signals start in this state, and if you forget to initialize some vectors to a value, they will be in that state.
'X' means unknown. It usually has two possible causes:
- you are trying to drive the signals from two places, one with '0' and one with '1'
- you are doing a logical operation with at least one of the input signals in the 'U', 'X', or 'Z' state
I think you should first give an initial value to all your signals. This ensures that you start in a good state. If then you still have 'X', it means that you are either driving the same signal from two places, or that you are reading a signal while it is in high impedance state ('Z'). I think that the latter is what is happening in your case, there is a one cycle delay between ft_din and rx_buf_in, so when you put rx_buf_re to 1 you are in fact putting in the FIFO the previous value of ft_din, which is in a high impedance state for at least one cycle.
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Hi, and first of all cheers for your help.
I have now delayed my rx_buf_we so that the write from ft_din to the rx_buf_in is one clock cycle later, but it doesn't seem to have done anything for the problem except to shift everything one clock cycle back.
I looked at my simulation to check which of my 'X' values were really X and which were U.
The rx_buf_in signal is just unitialised before it reads data, however the rx_buf_out signal is "XXXXXXXX" then when the rx buffers read enable goes high there is one clock where it stays "XXXXXXXX" then one clock of "UUUUUUUU" before it holds the test data expected.
On my transmit, before the data expected I also get 3 clock cycles of "XXXXXXXX" then one of "UUUUUUUU" before the expected test data is output from the tx buffer. I have a feeling that these bytes have been passed from the rx_buf_out signal though as the tx_buf_in is just uninitialised before having 3 bytes of "XXXXXXXX" one byte of "UUUUUUUU" then the expected data.
If I can sort out the data coming out of the RX buf then I think the bit on the TX_buffer will disappear.
Unfortunately I have very little to no experience of VHDL and FPGAs previous to this, so I'm learning as I go.... I am pretty sure that I am not driving these signals from two places, but have no idea why I am clocking out uninitialised bytes from one side of my FIFO to the other... Any things to look for? or things that may be common practise with FIFOs that I may have missed?
Cheers,
Lee H
Honored Contributor
