Problems with ModelSIM 2020.1 Starter Edition

Hi Gerhard,

Ya that method cannot save clock period. Sorry for confusion. For clock period you can declare it in testbench like below example:

`timescale 1ns/1ps

reg clk;

test uut(
.clk(clk));

...

initial begin

clk = 0;

forever begin

clk = #50 ~clk;

end

end

In this example the clock period is 100ns. You can try with 83.33ns.

Best Regards

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.