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Altera_Forum
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15 years ago

Problems with bidirectional signals in VHDL Testbench for ModelSim

Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, ...
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Altera_Forum
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12 years ago

Hello and Hi..Ia m Engineering student and working on VHDL for my Final Year Project..i have a problem in bidirectional data transfering...kindly help me to sort out the problem....

the problem is that i instantiate components in a top module and port map them in one direction.if want to port map them in second direction in same top module.....