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Altera_Forum
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15 years ago

Problems with bidirectional signals in VHDL Testbench for ModelSim

Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, ...
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Altera_Forum
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15 years ago

Just as a side note to tidy up the code: you could replace that process with:

AD <= testdata when N_OE = '0' else (others => 'Z');