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Altera_Forum
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15 years ago

Problems with bidirectional signals in VHDL Testbench for ModelSim

Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, ...
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Altera_Forum
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15 years ago

you process only runs once and then does nothing, so it is not changing during simulation. to fix it you need to do the following:

1. make the process sensive to "N_OE".

2. Delete the wait at the end of the process (you dont want any waits inside the process)

3. put the testdata assignment outside of the process.

This should make it work.