Problems with bidirectional signals in VHDL Testbench for ModelSim

Hmm... Still having a few problems with this... as I said I am very new to VHDL.

I can't avoid using the bidirectional signals/pins, as this is for the 245 Communication Interface between the Cyclone II and the FTDI FT2232H USB Bridge chip on the board. I am only trying to establish simple communications over USB and for now just echo back recieved characters.

This means to test my design I want my test bench to be able to input data into the AD[0..7] pins, then processed this data (in my design I am just trying to invert each bit of the byte for now) and then when its clear to transmit change AD[0..7] to outputs to output the data back to the FTDI chip (which puts the data into a transmit FIFO buffer to be send over USB.)

The output enable shown below "N_OE" is the output enable for the FTDI chip and so is used when reading from the FTDI chip, i.e. using AD[0..7] as inputs.

At the moment my values of AD[0..7] are now just appearing as either Z or X but not with any values on... The ammended code for my test bench is included...

Cheers

 
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "10/13/2010 16:36:17"
                                                            
-- Vhdl Test Bench template for design  :  Morph_USB_LOOPBACK
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 
LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                
ENTITY Morph_USB_LOOPBACK_vhd_tst IS
END Morph_USB_LOOPBACK_vhd_tst;
ARCHITECTURE Morph_USB_LOOPBACK_arch OF Morph_USB_LOOPBACK_vhd_tst IS
-- constants                                                 
-- signals  
SIGNAL testdata : STD_LOGIC_VECTOR(7 DOWNTO 0);                                                 
SIGNAL AC : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL AD : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL clkout : STD_LOGIC;
SIGNAL N_OE : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL siwua : STD_LOGIC;
COMPONENT Morph_USB_LOOPBACK
 PORT (
 AC : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
 AD : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 clkout : IN STD_LOGIC;
 N_OE : OUT STD_LOGIC;
 rst : IN STD_LOGIC;
 siwua : OUT STD_LOGIC
 );
END COMPONENT;
BEGIN
 i1 : Morph_USB_LOOPBACK
 PORT MAP (
-- list connections between master ports and signals
 AC => AC,
 AD => AD,
 clkout => clkout,
 N_OE => N_OE,
 rst => rst,
 siwua => siwua
 );
init : PROCESS                                               
-- variable declarations                                     
BEGIN  
 
 if (N_OE = '0') then
  AD <= testdata;
 else 
  AD <= "ZZZZZZZZ";
 end if;
 
 testdata <= "00000000", "10101010" after 166.6 NS, "11110000" after 499.8 NS;
 AC(0) <= '1', '0' after 183.2 NS,'1' after 266.2 NS, '0' after 582.8 NS, '1' after 665.8 NS;
 AC(1) <= '0', '0' after 333.2 NS, '1' after 499.8 NS, '1' after 582.8 NS;
 rst <= '0';
                  
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;                                          
END Morph_USB_LOOPBACK_arch;