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Altera_Forum
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15 years ago

Problems with bidirectional signals in VHDL Testbench for ModelSim

Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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you need to drive "ZZZZZZZZ" onto AD and AC when you expect signals to come out of the DUT.

Bidirectional signals are otherwise best avoided.

--- Quote End ---

Ah I knew I had to do something like this but was just trying to drive AD to 'Z' rather than "ZZZZZZZZ"...

Cheers, I'll give this a try...