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Altera_Forum
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15 years ago

Problems with bidirectional signals in VHDL Testbench for ModelSim

Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi,

Are you sure about your "bidirectional" design ? Have you wrote the 'z' for the case where your bidir is in inuput mode ?

'x' means forcing unkown : it is 0 or 1 but it often means that there is conflict. Your bidir is in ouput mode and your stimuli force this signal at the same time. (not verified myself, i may be wrong)

in quartus, you have templates available in menu when you edit vhdl.

In literature section on altera website, you will find example.

You have to check both your design and your testbench.

Keep in mind that VHDL is just a description langage (not a program).

Could you post your design and testbench ?