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Altera_Forum
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15 years ago

Problems with bidirectional signals in VHDL Testbench for ModelSim

Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, ...
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Altera_Forum
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15 years ago

Usually designers use bidirectional signals on pins and not internally.

input state: Your testbench should drive these pins when they are inputs to your DUT. Here your DUT can read them but should apply tristate(Z) i.e.cutoff logic.

output state:

Your DUT should drive them when they are outputs. testbench can read them.

The io blocks have tristate buffer that is switched off if Z applied. Internally no such buffer exists but can be emulated in logic but as mentioned, there is no need to use them internally.