Problems simulating ADC in DE10-Lite board using Quartus Prime Lite Edition 19.1 in VHDL designs, and at gate level in verilog designs

Thank you for your suggestions.

Our course is in VHDL, so we need to make designs in VHDL. Our students mainly work at home, so each student needs to install Quartus Prime in its PC or desktop. Standard version of Quartus Prime is a payment version, and students cannot buy it. This is the reason why, in the last years, we have been using the Lite version, which is free. In the past (some years ago), students used the Quartus II web version and asked for a semester licence, which was free.

In our design, we use variations of the Quartus Prime Lite IPs ALTPLL and modular ADC core, which are asked to be generated in VHDL. Nevertheless, only the top layers in the IP hierarchy are obtained in VHDL. Lower layers are obtained in verilog. This mixed VHDL/verilog is not supported by Modelsim in the Quartus Prime Lite version, so it is not possible to simulate at RTL level. It is possible to compile and simulate at gate level, but in this case the data out from the ADC is always 0, not following the expected behavior (the expected behavior only is found in verilog designs at RTL level).

Signal clkout_adccore still remains unconnected in synthesized modular ADC core when using Quartus Prime Lite 19.1, so you have to add the connection manually modifying the .vho file.

Any other suggestion? Thanks in advance.

Emili Lupon

emili.lupon@upc.edu