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Honored Contributor

17 years ago

Problem with VHDL code

Hi I'm really really new to VHDL codes and I'm having this problem with a very simple program of mine. The code is as shown below: library ieee; use ieee.std_logic_1164.all; use ieee.numeri...

Altera_Forum

Honored Contributor

17 years ago

Altera have some guidelines on coding for synthesis (which are pretty much the same as other FPGA manufacturers):

http://www.altera.com/literature/hb/...din g%20style (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=coding%20style)

I'd really recommend giving it a read - it will help you understand why you need to code synthesis things a certain way.

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Problem with VHDL code

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