Problem with VHDL code

Hi,

* I advice you to use reset_n to indicate an active low signal.

* to use std_(u)logic and std_(u)logic_vector only for ports

* Use indent for better readability (if not), comments (not too much)...

* You can find VHDL coding style in altera Web site or otherwhere.

* In process sensibility list (if it is not a process clk), you must enter all input process signals if you don't want to infer latches.

process (reset_n,order_n, input, a, b)

@Vernmid : there is NO clock signal. So no process(clk)

2) you should initialize all signals at reset_n and make reset_n the most priority signal

[darkred]begin

if reset_n = '0' then -- only reset_n

--all initializations here

total <= "00000000";

a <= 0;

b <= 0;

elsif enter_n = '1' then -- (obviously reset_n = '1')

a <= input;

b <= total;

else -- imply (enter = '0' and reset = '1')

total <= a + b;

end if;

end process;

* The behaviour above is asynchronous : you have glitches, combin. loops (very instable), sometimes latches.

Very hard to debug if contains loops.

Asynchronous design is usually used to make decoders, MUX, RS, tristate bus ...

As Vernmid said, you are recommanded to use

process(reset_n, clk)
begin
if reset_n = '0' then 
...
elsif rising_edge(clk) then
if enter_n = '0' then
...
else
...
end if;
end if;
end process;

Quartus give templates.

Keep in mind that you create logic design.

May the force be with you :-)