--- Quote Start ---
process (enter,reset)
begin
if (reset = '0' and enter = '1') then
total <= "00000000";
end if;
if (enter = '1' and reset = '1') then
a <= input;
b <= total;
elsif (enter = '0' and reset = '1') then
total <= a + b;
end if;
end process;
--- Quote End ---
You are trying to imply storage i.e. a FlipFlop for and b.
The process above is not correct coding for a synchronous process and hence will not synthesize to any flipflops.
I suggest you read up about synchronous design for VHDL.
BUT....
Something like
process (clk)
begin
if (clk'event and clk= '1') then
if (reset = '0' and enter = '1') then
total <= "00000000";
elsif (enter = '1' and reset = '1') then
a <= input;
b <= total;
elsif (enter = '0' and reset = '1') then
total <= a + b;
end if;
end if;
end process;
might be a start.
The line if (clk'event and clk= '1') then effectively means wait for a rising edge on the clk signal.
You will need to provide a clock generator to your design.
Hope this gives you some clues!
Let me know how you get on
Honored Contributor
