Altera_Forum
Honored Contributor
Honored Contributorproblem with vga
back here again with a problem and I hope you can help me as I said to the vga not want to send the colors on the screen active only vh_sync
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ENTITY VGA IS PORT( CLOCK_24: IN STD_LOGIC_VECTOR(1 downto 0); VGA_HS,VGA_VS: OUT STD_LOGIC; VGA_R,VGA_G,VGA_B: OUT STD_LOGIC_VECTOR(3 downto 0); KEY: IN STD_LOGIC_VECTOR(3 downto 0); SW : IN STD_LOGIC_VECTOR(1 downto 0) ); END VGA; ARCHITECTURE MAIN OF VGA IS SIGNAL VGACLK,RESET: STD_LOGIC:='0'; --------------------------------------------- component PLL is port ( clk_in_clk : in std_logic := 'X'; -- clk reset_reset : in std_logic := 'X'; -- reset clk_out_clk : out std_logic -- clk ); end component PLL; -------------------------------------------- COMPONENT SYNC IS PORT( CLK: IN STD_LOGIC; HSYNC,VSYNC: OUT STD_LOGIC; R,G,B : OUT STD_LOGIC_VECTOR(3 downto 0); KEYS: IN STD_LOGIC_VECTOR(3 downto 0); S: IN STD_LOGIC_VECTOR(1 downto 0) ); END COMPONENT SYNC; BEGIN C1: SYNC PORT MAP(VGACLK,VGA_HS,VGA_VS,VGA_R,VGA_G,VGA_B,KEY,SW); C2: PLL PORT MAP(CLOCK_24(0),RESET,VGACLK); END MAIN; ------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.my.all; ENTITY SYNC IS PORT( CLK: IN STD_LOGIC; HSYNC,VSYNC: OUT STD_LOGIC; R,G,B : OUT STD_LOGIC_VECTOR(3 downto 0); KEYS: IN STD_LOGIC_VECTOR(3 downto 0); S: IN STD_LOGIC_VECTOR(1 downto 0) ); END SYNC; ARCHITECTURE MAIN OF SYNC IS SIGNAL RGB: STD_LOGIC_VECTOR(3 downto 0); SIGNAL DRAW,DRAW2: STD_LOGIC; SIGNAL SQ_X1,SQ_Y1: INTEGER RANGE 0 TO 1712:=200; SIGNAL SQ_X2,SQ_Y2: INTEGER RANGE 0 TO 1712:=400; SIGNAL HPOS: INTEGER RANGE 0 TO 1712:=0; SIGNAL VPOS: INTEGER RANGE 0 TO 994:=0; BEGIN SQ(HPOS,VPOS,SQ_X1,SQ_Y1,RGB,DRAW); SQ(HPOS,VPOS,SQ_X2,SQ_Y2,RGB,DRAW2); PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN IF(DRAW='1')THEN IF(S(0)='1')THEN R<=(OTHERS=>'1'); G<=(OTHERS=>'0'); B<=(OTHERS=>'0'); ELSE R<=(OTHERS=>'1'); G<=(OTHERS=>'1'); B<=(OTHERS=>'1'); END IF; END IF; IF(DRAW2='1')THEN IF(S(1)='1')THEN R<=(OTHERS=>'1'); G<=(OTHERS=>'0'); B<=(OTHERS=>'0'); ELSE R<=(OTHERS=>'1'); G<=(OTHERS=>'1'); B<=(OTHERS=>'1'); END IF; END IF; IF(DRAW='0' AND DRAW2='0')THEN R<=(OTHERS=>'1'); G<=(OTHERS=>'0'); B<=(OTHERS=>'0'); END IF; IF(HPOS<1712)THEN HPOS<=HPOS+1; ELSE HPOS<=0; IF(VPOS<994)THEN VPOS<=VPOS+1; ELSE IF(S(0)='1')THEN IF(KEYS(0)='0')THEN SQ_X1<=SQ_X1+5; END IF; IF(KEYS(1)='0')THEN SQ_X1<=SQ_X1-5; END IF; IF(KEYS(2)='0')THEN SQ_Y1<=SQ_Y1+5; END IF; IF(KEYS(3)='0')THEN SQ_Y1<=SQ_Y1-5; END IF; END IF; IF(S(1)='1')THEN IF(KEYS(0)='0')THEN SQ_X2<=SQ_X2+5; END IF; IF(KEYS(1)='0')THEN SQ_X2<=SQ_X2-5; END IF; IF(KEYS(2)='0')THEN SQ_Y2<=SQ_Y2+5; END IF; IF(KEYS(3)='0')THEN SQ_Y2<=SQ_Y2-5; END IF; END IF; VPOS<=0; END IF; END IF; IF(HPOS>80 AND HPOS<216)THEN HSYNC<='0'; ELSE HSYNC<='1'; END IF; IF(VPOS>1 AND VPOS<30)THEN VSYNC<='0'; ELSE VSYNC<='1'; END IF; IF((HPOS>0 AND HPOS<432)OR(VPOS>0 AND VPOS<34))THEN R<=(OTHERS=>'0'); G<=(OTHERS=>'1'); B<=(OTHERS=>'1'); END IF; END IF; END PROCESS; END MAIN; -------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; PACKAGE MY IS PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos: IN INTEGER;SIGNAL RGB:OUT STD_LOGIC_VECTOR(3 downto 0);SIGNAL DRAW: OUT STD_LOGIC); END MY; PACKAGE BODY MY IS PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos: IN INTEGER;SIGNAL RGB:OUT STD_LOGIC_VECTOR(3 downto 0);SIGNAL DRAW: OUT STD_LOGIC) IS BEGIN IF(Xcur>Xpos AND Xcur<(Xpos+200) AND Ycur>Ypos AND Ycur<(Ypos+200))THEN RGB<="1111"; DRAW<='1'; END IF; END SQ; END MY;
