Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

problem with value 'X' in VHDL

Dear my best friends I used vhdl to calculate SVPWM algorithm. I used LPM library for divider. I'd already initial value for all of signal, but It still has "X" value. This is LPM library m0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

it is a bad practice to assign a signal in that way.

--- Quote End ---

In my opinion, This do not redundant code because I use it in different clock, first clock I sign the value TTA and T_sum for A and B, next clock I get the result of A/B. after that I sign the value TTB and T_sum to A and B again and next clock I get the result of A/B.

You can see my first post in this thread