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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem with value 'X' in VHDL

Dear my best friends I used vhdl to calculate SVPWM algorithm. I used LPM library for divider. I'd already initial value for all of signal, but It still has "X" value. This is LPM library m0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

'Z' just means high impedance, which is odd for an input. It will probably connect it to '0' when its synthesized.

The output should be correct.

Alternativly, just do

addr <= adda + addb;

in your code