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Altera_Forum
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15 years ago

Problem with Synthese in Quartus with Customer-IP vhdl-file

Hi All, I make a Customer IP and when I wont make a synthese, I have following error-message: Error (10820): Netlist error at ime_avalon_xy_detector.vhd(109): can't infer register for coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi std_logic_vector

<< I dont know if coe_iVGA_HS and coe_iVGA_CLK are asynchronous. If they << are, take measures for clock domain crossing.

coe_iVGA_HS and coe_iVGA_CLK are synchronous, that are not problem...

Bye ;)