Problem with Synthese in Quartus with Customer-IP vhdl-file

Hi Antonio,

You use two clocks in one process (coe_iVHA_HS and coe_iVGA_CLK). Like you said that could work in simulation, but how would a hardware implementation look like?

I would make a seperate process for the flag_hs signal, which look like:

process(coe_iVGA_HS, coe_iRST_N, reset_hs_flag)

begin if coe_iRST_N = '0' or reset_hs = '1' then

flag_hs <= '0';

[/INDENT] elsif(coe_iVGA_HS = '1' AND coe_iVGA_HS'event) then

flag_hs <= '1';

[/INDENT] end if;

end process;

define a signal reset_hs_flag and change

line 112 to reset_hs_flag <= '0';

line 125 to reset_hs_flag <= '1';

Remove lines 116 and 117.

I dont know if coe_iVGA_HS and coe_iVGA_CLK are asynchronous. If they are, take measures for clock domain crossing.

Succes, Ton