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lkarp1's avatar
lkarp1
Icon for New Contributor rankNew Contributor
5 years ago

Problem with Quartus Prime 20.3/20.2 on Cyclone 10GX Missing 2.5/3.0V IO Standard in pin planer

Hello, I am building design where I need 3.0V TTL signals to connect to processor. Problem is Quartus Pin planner does not even have option to select 3.0V LVCMOS or LVTTL. While I can do it by ha...
lkarp1's avatar
lkarp1
Icon for New Contributor rankNew Contributor
5 years ago

Hello, Thank you for correct response.
Well, tats is very disappointing...

That is big problem for me. I was used to that I can connect IO bank too any voltage and get same CMOS voltage out of it. But what kind of limitation does GX part has ? This is not a problem for regular Cyclone 10 LP for same footprint and cell size.

Usually true LVDS banks are missing and 3V CMOS are abundant , but I see now that with this chip, is other way around. all FPGA's can only have 48x 3V capable pins.

Now just have to figure out how to make this work.

Thank you for support!

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Linas

Since the question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei