New Contributor
Super ContributorAccording to figure 67 and table 36, your 10CX105 only supports 3 V in I/O bank 2L, not in 3A or 3B like you show in your video. Table 33 shows that 3 V is only allowed in the 3 V I/O not the LVDS I/O.
New ContributorHello, Thank you for correct response.
Well, tats is very disappointing...
That is big problem for me. I was used to that I can connect IO bank too any voltage and get same CMOS voltage out of it. But what kind of limitation does GX part has ? This is not a problem for regular Cyclone 10 LP for same footprint and cell size.
Usually true LVDS banks are missing and 3V CMOS are abundant , but I see now that with this chip, is other way around. all FPGA's can only have 48x 3V capable pins.
Now just have to figure out how to make this work.
Thank you for support!
Frequent ContributorHi Linas
Since the question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
