Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHey Tareq,
I'm new to Quartus II as well, but I have found an easier way to run gate level simulation with ModelSim. Basically the idea is to use leverage NativeLink built-in Quartus II that supports running testbench with the bundled ModelSim Altera Edition. NativeLink allows you to launch top level simulation in ModelSim Altera without having to type anything in ModelSim console. This saves a bit of time and also streamlines the flow. NativeLink settings can be found in Assignments > Settings > EDA Tool Settings > Simulation. Make sure you select ModelSim-Altera as your simulation tool under Assignments > Settings > EDA Tool Settings. The flow is as follows: (1) Write your design files in HDL of your choice (verilog/VHDL). Then write your testbench, save the testbench in the same folder, and you don't necessary have to add it to the project. (2) Go to Assignments > Settings > EDA Tool Settings > Simulation, click on "Compile test bench radio button in NativeLink Settings". Click on Test Benches button to add your testbench code. Make sure you check Generate Value Change Dump file script and make sure your design instance name matches the one you entered in Test Bench Settings. (3) Compile your design (4) Tool > Run EDA Simulation Tool > EDA Gate Level Simulation (5) In ModelSim-Altera console, type <design_name>_dump_all_vcd_nodes.tcl, and hit enter. This will generate the VCD file you need for powerplay power estimation. You can also just type <design_name> and scroll down from the selection menu, _dump_all_vcd_nodes.tcl should be one of the options. Hope this helps. So far this flow has saved me some headache from figuring out how to run ModelSim-Altera from ground up.