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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with PowerPlay Power Analyser

Hi, I am new to FPGA world. I want to measure power by Quartus PowerPlay of an 8 bit counter. I simulated it with a test bench in ModelSim and generated VCD file. (Attached: counter.vhd) I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think the net-list that you are using to generate the VCD file is that or RTL level and not gate-level.

Try to generate a gate level net list (.vo) file for your counter use it instead of your .v file in the simulation then generate the vcd file and I think it would increase the confidence level.