problem with modelsim for postsimulation

Hi feizhang,

a negative value for clock skew?

For what I know a negative value on clock skew tends to exacerbate setup timing problems. But as you said that your design only runs at 6 MHz this should not be the problem.

Let's try to go to the basics:

1) Is your design fully synchronous (every flip flop clocked from the same clk signal)?

2) Did you remove all the latches?

3) Did you put a flip flop on every input signal before any logic?

If the answer is yes to all the question then the problem is not easy to solve...