Honored Contributor
Honored ContributorI used to smartTime to analyze my code, and I have no idea how to use it. Currently, I did not find the negative slacks. but found negative value on skew as follows. I don't know what it means.
Source Pin Sink Pin Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Skew (ns) 1 CC_counter/Q[2]:CLK x[5] 13.249 64.240 16.496 80.736 1.112 27.770 -0.476 2 CC_counter/Q[2]:CLK q_1[7]:E 13.023 64.317 16.270 80.587 1.289 27.616 -0.504 3 CC_counter/Q[0]:CLK x[5] 13.071 64.418 16.318 80.736 1.112 27.414 -0.476 4 CC_counter/Q[2]:CLK q_1[4]:E 12.951 64.529 16.198 80.727 1.289 27.192 -0.644 5 CC_counter/Q[0]:CLK x[3] 13.029 64.582 16.276 80.858 1.112 27.086 -0.598 6 CC_counter/Q[2]:CLK q_1[2]:E 12.710 64.630 15.957 80.587 1.289 26.990 -0.504 7 CC_counter/Q[1]:CLK x[6] 12.830 64.659 16.077 80.736 1.112 26.932 -0.476 8 CC_counter/Q_0[1]:CLK x[5] 12.569 64.920 15.816 80.736 1.112 26.410 -0.476 9 CC_counter/Q[1]:CLK x[5] 12.569 64.920 15.816 80.736 1.112 26.410 -0.476 10 CC_counter/Q_0[1]:CLK x[3] 12.527 65.084 15.774 80.858 1.112 26.082 -0.598 11 CC_counter/Q[0]:CLK out2[2]:E 12.127 65.191 15.374 80.565 1.289 25.868 -0.482 12 CC_counter/Q[2]:CLK x[3] 12.392 65.219 15.639 80.858 1.112 25.812 -0.598 13 CC_counter/Q[1]:CLK x[4] 12.257 65.275 15.504 80.779 1.112 25.700 -0.519 14 CC_counter/Q[0]:CLK x[6] 12.188 65.301 15.435 80.736 1.112 25.648 -0.476 15 CC_counter/Q[0]:CLK q_1[7]:E 11.997 65.343 15.244 80.587 1.289 25.564 -0.504 16 CC_counter/Q[0]:CLK y[0]:E 12.320 65.350 15.567 80.917 0.947 25.550 -0.492 17 CC_counter/Q[1]:CLK x[3] 12.228 65.383 15.475 80.858 1.112 25.484 -0.598 18 CC_counter/Q[2]:CLK q_1[1]:E 11.875 65.464 15.122 80.586 1.289 25.322 -0.503 19 CC_counter/Q[2]:CLK x[7] 12.016 65.480 15.263 80.743 1.148 25.290 -0.519 20 CC_counter/Q[2]:CLK x[2] 11.917 65.525 15.164 80.689 1.148 25.200 -0.465 21 CC_counter/Q[0]:CLK q_1[4]:E 11.925 65.555 15.172 80.727 1.289 25.140 -0.644 22 CC_counter/Q[0]:CLK out2[4]:E 11.830 65.650 15.077 80.727 1.289 24.950 -0.644 23 CC_counter/Q[0]:CLK q_1[2]:E 11.684 65.656 14.931 80.587 1.289 24.938 -0.504 24 CC_counter/Q[0]:CLK out2[5]:E 11.780 65.702 15.027 80.729 1.289 24.846 -0.646 25 CC_counter/Q[1]:CLK x[2] 11.762 65.716 15.009 80.725 1.112 24.818 -0.465 26 CC_counter/Q[1]:CLK x[0] 11.855 65.764 15.102 80.866 1.112 24.722 -0.606 27 CC_counter/Q[2]:CLK q_1[5]:E 11.666 65.788 14.913 80.701 1.289 24.674 -0.618 28 CC_counter/Q[2]:CLK x[6] 11.664 65.825 14.911 80.736 1.112 24.600 -0.476 29 CC_counter/Q[1]:CLK out2[2]:E 11.483 65.835 14.730 80.565 1.289 24.580 -0.482 30 CC_counter/Q[1]:CLK x[7] 11.657 65.875 14.904 80.779 1.112 24.500 -0.519 31 CC_counter/Q[2]:CLK q_1[6]:E 11.568 65.886 14.815 80.701 1.289 24.478 -0.618 32 CC_counter/Q[0]:CLK out2[3]:E 11.488 65.895 14.735 80.630 1.289 24.460 -0.547 33 CC_counter/Q[0]:CLK out2[6]:E 11.488 65.895 14.735 80.630 1.289 24.460 -0.547 34 CC_counter/Q[2]:CLK x[1] 11.578 65.912 14.825 80.737 1.148 24.426 -0.513 35 CC_counter/Q[0]:CLK x[4] 11.615 65.917 14.862 80.779 1.112 24.416 -0.519 36 CC_counter/Q[0]:CLK out2[0]:E 11.335 65.988 14.582 80.570 1.289 24.274 -0.487 37 CC_counter/Q[1]:CLK y[0]:E 11.676 65.994 14.923 80.917 0.947 24.262 -0.492 38 CC_counter/Q[2]:CLK x[4]:D 11.446 66.050 14.693 80.743 1.148 24.150 -0.519 39 CC_counter/Q[0]:CLK out2[7]:E 11.307 66.076 14.554 80.630 1.289 24.098 -0.547 40 CC_counter/Q_0[1]:CLK x[6] 11.397 66.092 14.644 80.736 1.112 24.066 -0.476 41 register1/Q[5]:CLK x[5] 11.393 66.136 14.600 80.736 1.112 23.978 -0.516 42 CC_counter/Q[0]:CLK x[2] 11.324 66.154 14.571 80.725 1.112 23.942 -0.465 43 CC_counter/Q[2]:CLK x[0] 11.345 66.238 14.592 80.830 1.148 23.774 -0.606 44 CC_counter/Q[2]:CLK p0[2]:E 11.095 66.267 14.342 80.609 1.289 23.716 -0.526 45 CC_counter/Q[2]:CLK p0[4]:E 11.085 66.291 14.332 80.623 1.289 23.668 -0.540 46 CC_counter/Q[1]:CLK p0[2]:E 11.070 66.292 14.317 80.609 1.289 23.666 -0.526 47 CC_counter/Q[1]:CLK out2[4]:E 11.186 66.294 14.433 80.727 1.289 23.662 -0.644 48 CC_counter/Q[1]:CLK p0[4]:E 11.060 66.316 14.307 80.623 1.289 23.618 -0.540 49 CC_counter/Q[1]:CLK out2[5]:E 11.136 66.346 14.383 80.729 1.289 23.558 -0.646 50 CC_counter/Q[2]:CLK p0[5]:E 11.102 66.378 14.349 80.727 1.289 23.494 -0.644 51 CC_counter/Q[0]:CLK x[0] 11.226 66.393 14.473 80.866 1.112 23.464 -0.606 52 CC_counter/Q[1]:CLK p0[5]:E 11.077 66.403 14.324 80.727 1.289 23.444 -0.644 53 CC_counter/Q[0]:CLK y[4]:E 11.303 66.415 14.550 80.965 0.947 23.420 -0.540 54 CC_counter/Q[2]:CLK q_1[0]:E 10.927 66.421 14.174 80.595 1.289 23.408 -0.512 55 CC_counter/Q[2]:CLK p0[6]:E 11.010 66.444 14.257 80.701 1.289 23.362 -0.618 56 CC_counter/Q[1]:CLK q_1[7]:E 10.884 66.456 14.131 80.587 1.289 23.338 -0.504 57 CC_counter/Q[1]:CLK p0[6]:E 10.985 66.469 14.232 80.701 1.289 23.312 -0.618 58 CC_counter/Q[0]:CLK q_1[1]:E 10.849 66.490 14.096 80.586 1.289 23.270 -0.503 59 CC_counter/Q[0]:CLK out2[1]:E 10.835 66.501 14.082 80.583 1.289 23.248 -0.500 60 CC_counter/Q[0]:CLK x[7] 10.990 66.506 14.237 80.743 1.148 23.238 -0.519 61 CC_counter/Q[0]:CLK y[3]:E 11.127 66.517 14.374 80.891 0.947 23.216 -0.466 62 CC_counter/Q[2]:CLK p0[3]:E 10.881 66.518 14.128 80.646 1.289 23.214 -0.563 63 CC_counter/Q[1]:CLK out2[3]:E 10.844 66.539 14.091 80.630 1.289 23.172 -0.547 Source Pin Sink Pin Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) 1 y[4]:CLK w[3] 81.720 85.507 85.507 2 y[4]:CLK w[6] 81.300 85.087 85.087 3 y[5]:CLK w[3] 81.192 84.979 84.979 4 y[4]:CLK w[5] 81.035 84.822 84.822 5 A[0]:CLK w[3] 81.027 84.814 84.814 6 A[1]:CLK w[3] 81.017 84.804 84.804 7 y[5]:CLK w[6] 80.772 84.559 84.559 8 y[4]:CLK w[4] 80.655 84.442 84.442 9 A[0]:CLK w[6] 80.607 84.394 84.394 10 A[1]:CLK w[6] 80.597 84.384 84.384 11 y[5]:CLK w[5] 80.507 84.294 84.294 12 y[2]:CLK w[3] 80.279 84.172 84.172 13 A[0]:CLK w[5] 80.342 84.129 84.129 14 A[1]:CLK w[5] 80.332 84.119 84.119 15 y[5]:CLK w[4] 80.127 83.914 83.914 16 y[4]:CLK w[2] 80.060 83.847 83.847 17 y[6]:CLK w[3] 79.931 83.822 83.822 18 y[4]:CLK w[1] 79.994 83.781 83.781 19 y[2]:CLK w[6] 79.859 83.752 83.752 20 A[0]:CLK w[4] 79.962 83.749 83.749 21 A[1]:CLK w[4] 79.952 83.739 83.739 22 y[1]:CLK w[3] 79.709 83.496 83.496 23 y[2]:CLK w[5] 79.594 83.487 83.487 24 y[3]:CLK w[3] 79.739 83.452 83.452 25 y[6]:CLK w[6] 79.511 83.402 83.402 26 y[5]:CLK w[2] 79.532 83.319 83.319 27 y[5]:CLK w[1] 79.466 83.253 83.253 28 A[0]:CLK w[2] 79.367 83.154 83.154 29 A[1]:CLK w[2] 79.357 83.144 83.144 30 y[6]:CLK w[5] 79.246 83.137 83.137 31 y[2]:CLK w[4] 79.214 83.107 83.107 32 A[0]:CLK w[1] 79.301 83.088 83.088 33 A[1]:CLK w[1] 79.291 83.078 83.078 34 y[1]:CLK w[6] 79.289 83.076 83.076 35 y[3]:CLK w[6] 79.319 83.032 83.032 36 y[1]:CLK w[5] 79.024 82.811 82.811 37 y[3]:CLK w[5] 79.054 82.767 82.767 38 y[6]:CLK w[4] 78.866 82.757 82.757 39 y[2]:CLK w[2] 78.619 82.512 82.512 40 y[2]:CLK w[1] 78.553 82.446 82.446 41 y[1]:CLK w[4] 78.644 82.431 82.431 42 y[3]:CLK w[4] 78.674 82.387 82.387 43 y[0]:CLK w[3] 78.606 82.345 82.345 44 A[2]:CLK w[3] 78.535 82.322 82.322 45 y[6]:CLK w[2] 78.271 82.162 82.162 46 y[6]:CLK w[1] 78.205 82.096 82.096 47 y[0]:CLK w[6] 78.186 81.925 81.925 48 A[2]:CLK w[6] 78.115 81.902 81.902 49 y[1]:CLK w[2] 78.049 81.836 81.836 50 y[3]:CLK w[2] 78.079 81.792 81.792 51 y[1]:CLK w[1] 77.983 81.770 81.770 52 y[3]:CLK w[1] 78.013 81.726 81.726 53 y[0]:CLK w[5] 77.921 81.660 81.660 54 A[2]:CLK w[5] 77.850 81.637 81.637 55 y[0]:CLK w[4] 77.541 81.280 81.280 56 A[2]:CLK w[4] 77.470 81.257 81.257 57 y[0]:CLK w[2] 76.946 80.685 80.685 58 A[2]:CLK w[2] 76.875 80.662 80.662 59 y[0]:CLK w[1] 76.880 80.619 80.619
