Honored Contributor
Honored ContributorI found this explanation for this problem as follows, but can not understand it well and am not sure whether this problem needs obsolute revision and how to revise it? Obvisouly, my prolem is the pulse width. Please suggest this if you can. Thanks.
Timing Violation errors or warnings during post layout simulation. For example, take the error message:# ** Error: C:/Actel/Libero_v8.5/Model/win32acoem/../../Designer/lib/modelsim/precompiled/ vlog/src/54sxa.v(8363): $setup( posedge D:30272700 ps, posedge CLK &&& Enable1:30273400 ps, 900 ps );# Time: 30273400 ps Iteration: 1 Instance: /testbench/NJFPGA_0/\$1I255 /\$1I227 The Error Messages contained in the ModelSim Simulation Error Log is actually timing violation errors notifying you about timing violations in a post-layout Back Annotated Timing Simulation with respect to the setup, hold, and pulse width restrictions specified in the device library and in the SDF Timing Delay file for the design under test. You must evaluate each message and determine if there is a legitimate timing issue with the design that will cause the design not to function or whether you can ignore certain errors. The example error says that Instance /testbench/NJFPGA_0/\$1I255 /\$1I227 of the design shows a setup time violation on the positive edge of a filp-flop. It shows that the minimum setup time on the D port is 900ps, but from the simulation, only 700ps setup time is used (posedge of D at 30272700ps while posedge of CLK comes at 30273400ps). These checks are coded into the device library source file and the delays for the specific instances of the design are in the SDF file.
